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| Features * * * * * * * * * * * Fully Integrated Low IF Receiver Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 kBit/s High Sensitivity of Typically -93 dBm Due to Integrated LNA High Output Power of Typically +4 dBm Multi-channel Operation - 95 Channels - Support Frequency Hopping (ETSI) and Digital Modulation (FCC) Supply-voltage Range 2.9 V to 3.6 V (Unregulated) Auxiliary-voltage Regulator on Chip (3.2 V to 4.6 V) Low Current Consumption Few Low Cost External Components Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier Low Profile Lead-free Plastic Package QFN32 (5 x 5 x 0.9 mm) Low IF 2.4 GHz ISM Transceiver ATR2406 Applications * * * * * * * Hightech Multi-user Toys Wireless Game Controllers Telemetry Wireless Audio/Video Electronic Point of Sales Wireless Head Set FCC CFR47, Part 15, ETSI EN 300 328 and ARIB STD-T-66 Compliant Radio Links Preliminary Electrostatic sensitive device. Observe precautions for handling. Description The ATR2406 is a single chip RF-transceiver intended for applications in the 2.4 GHz ISM band. The QFN32 packaged IC is a complete transceiver including image rejection mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF-transceiver offers a clock recovery function on-chip. Rev. 4779F-ISM-09/04 Figure 1. Block Diagram REG_DEC VREG REG_CTRL VS_REG IREF VS_SYN VS_IFD VS_IFA VS_RX/TX LIMITER RSSI DEMOD VREG_VCO VCO REG AUX REG VREF LNA IR-MIXER BP RX_IN RX_DATA RSSI PA VCO BUS TX_OUT CLOCK DATA ENABLE RAMP_OUT RAMP GEN GAUSSIAN FILTER PLL CTRL LOGIC RX-CLOCK PU_REG PU_TRX RX_ON TX_ON nOLE CP REF_CLK TX_DATA VTUNE Pin Configuration Figure 2. Pinning QFN32 - 5 x 5 ENABLE DATA CLOCK TX_DATA RX_DATA PU_TRX nOLE TX_ON PU_REG REF_CLK RSSI VS_IFD VS_IFA RX-CLOCK IC IREF 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 ATR2406 RX_ON IC IC RAMP_OUT TX_OUT RX_IN1 RX_IN2 VS_TRX 2 ATR2406 [Preliminary] 4779F-ISM-09/04 REG_CTRL VREG VS_REG REG_DEC VREG_VCO VTUNE CP VS_SYN ATR2406 [Preliminary] Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Paddle Symbol PU_REG REF_CLK RSSI VS_IFD VS_IFA RX-CLOCK IC IREF REG_CTRL VREG VS_REG REG_DEC VREG_VCO VTUNE CP VS_SYN VS_TRX RX_IN2 RX_IN1 TX_OUT RAMP_OUT IC IC RX_ON TX_ON nOLE PU_TRX RX_DATA TX_DATA CLOCK DATA ENABLE GND Function Power-up input for auxiliary regulator Reference frequency input Received signal strength indicator output Digital supply voltage Analog supply voltage for IF circuits RX-CLOCK, if RX mode with clock recovery is active Internal connected, do not connect on PCB External resistor for band-gap reference Auxiliary voltage regulator control output Auxiliary voltage regulator output Auxiliary voltage regulator supply voltage Decoupling pin for VCO_REG VCO voltage regulator VCO tuning voltage input Charge-pump output Synchronous supply voltage Transmitter receiver supply voltage Differential receiver input 2 Differential receiver input 1 TX driver amplifier output Ramp generator output for PA power ramping Internal connected, do not connect on PCB Internal connected, do not connect on PCB RX control input TX control input Open loop enable input RX/TX/PLL/VCO power-up input RX data output TX data input 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input Ground 3 4779F-ISM-09/04 Functional Description Receiver The RF signal at RF_IN is differently fed through the LNA to the image rejection mixer IR_MIXER driving the integrated LowIF bandpass filter. The IF frequency is 864 kHz.The limiting IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator DEMOD. No tuning is required. Datasling is handled internally. For 1152 kBit/s data rate the receiver has a clock recovery function on-chip. The receiver includes a clock recovery circuit which regenerates the clock out of the received data. The advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data) which allows to reduce the load of the processing microcontroller significantly. The falling edge of the clock gives the optimal sampling position for the RX_Data signal so at this event the data must be sampled by the microcontroller. The recovered clock is available at pin 6. Clock Recovery Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typically +4 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled internally so that spurious requirements are fulfilled. Synthesizer The IR_MIXER, the PA and the programmable counter PC are driven by the fully integrated VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 1.728 MHz). Open loop modulation is supported. An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. Power Supply 4 ATR2406 [Preliminary] 4779F-ISM-09/04 ATR2406 [Preliminary] Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage auxiliary regulator Supply voltage Control voltages Storage temperature Input RF level ESD protection Symbol VS VS Vcontr Tstg PRF VESD_anal VESD_dig Min. -0.3 -0.3 -0.3 -40 Max. +4.7 +3.6 VS +125 +10 TBD TBD Unit V V V C dBm V V Operating Range Parameters Supply voltage Auxiliary regulator supply voltage Temperature ambient Input frequency range Symbol VS VS_BATT Tamb fRX Min. 2.9 3.2 -10 2400 Max. 3.6 4.6 +60 2483 Unit V V C MHz Electrical Characteristics VS = 3.6 V with AUX regulator, Tamb = 25C, unless otherwise specified No. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 2.1 2.2 3 3.1 3.2 Notes: Parameters Supply Supply voltage Supply voltage RX supply current TX supply current Synthesizer supply current Supply current in power-down mode Supply current in power-down mode Voltage Regulator AUX regulator VCO regulator Transmitter Part TX data rate Output power Over full temperature range, from 2400 MHz to 2483 MHz(1) PTX 72/144/288/576/1152 0 4 kBit/s dBm VREG VREG_VCO 3.0 2.7 V V With AUX regulator PU_TRX = 0; PU_REG = 0 w/o AUX regulator PU_TRX = 0; PU_REG = 0 With AUX regulator w/o AUX regulator CW-mode CW-mode VS VS IS IS IS IS IS 3.2 2.9 3.6 3.0 31 16 26 <1 <1 4.6 3.6 V V mA mA mA A A Test Conditions Symbol Min. Typ. Max. Unit 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For further information refer to Application Note. 5 4779F-ISM-09/04 Electrical Characteristics (Continued) VS = 3.6 V with AUX regulator, Tamb = 25C, unless otherwise specified No. 3.3 3.4 3.5 3.6 3.7 Parameters TX data filter clock Frequency deviation Frequency deviation scaling Frequency drift during a slot Harmonics 2nd Harmonic 3rd Harmonic Spurious Emission 30 - 1000 MHz 1 - 12.75 GHz 1.8 - 1.9 GHz 5.15 - 5.3 GHz Receiver Part Sensitivity Third order input intercept point Intermodulation rejection Co-channel rejection BER < 10 , wanted at -83 dBm, level of interferers in channels N + 2 and N + 4(1) BER < 10-3, wanted at -76 dBm(1) BER < 10 , wanted at -76 dBm, adjacent level referred to wanted channel level(1) 1.728 MHz BER < 10-3, wanted at -76 dBm, biadjacent level referred to wanted channel level(1) 3.456 MHz BER < 10-3, wanted at -76 dBm, n 3 adjacent level referred to wanted channel level(1) 5.128 MHz BER < 10-3, wanted at -83 dBm at 2.45 GHz(1) BER < 10-3, wanted at -83 dBm at 2.45 GHz(1) BER < 10-3, wanted at -83 dBm at 2.45 GHz(1) -3 -3 Test Conditions 6 taps in filter GFFM = GFFM_nom x GFCS (see bus protocol D9 to D11) Symbol fTXFCLK GFFM_nom GFCS fo (drift) Min. Typ. 6.912 400 Max. Unit MHz kHz 60 130 10 -40.5 -46 -40.5 -48 -70 -70 % kHz dBc dBc dBm dBm dBm dBm BW = 100 kHz(1) 3.8 BW = 100 kHz(1) 4 4.1 4.2 4.3 4.4 At input for BER 10-3 at 1152 kBit/s(1) IIP3 IM3 RCO Ri (N-1) 32 -11 -93 -15 dBm dBm dBc dBc 4.5 Adjacent channel rejection 4 dBc 4.6 Bi-adjacent channel rejection Ri (N - 2) 30 dBc 4.7 Rejection with 3 channels separation Ri (n 3) 40 dBc 4.8 Out of band rejection > 6 MHz Out of band rejection 2300 MHz to 2394 MHz 2506 MHz to 2600 GHz Bldf>6MHz 38 dBc 4.9 Blnear 47 dBc Out of band rejection 4.10 30 MHz to 2300 MHz 2600 MHz to 6 GHz 5 5.1 Notes: RSSI Part Maximum RSSI output voltage Blfar 57 dBc Under high RX input signal level VRSSImax 2.1 V 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For further information refer to Application Note. 6 ATR2406 [Preliminary] 4779F-ISM-09/04 ATR2406 [Preliminary] Electrical Characteristics (Continued) VS = 3.6 V with AUX regulator, Tamb = 25C, unless otherwise specified No. 5.2 5.3 6 6.1 6.2 6.3 7 7.1 7.2 7.3 7.4 7.5 8 8.1 9 9.1 9.2 10 Parameters Test Conditions Symbol VRSSI Ton Min. Typ. 1.9 0.3 40 Max. Unit V V s RSSI output voltage, monotonic with -33 dBm at RF input over range -96 dBm to -36 dBm with -96 dBm at RF input Wake-up time from power-up signal to correct RSSI output VCO Oscillator frequency Frequency control voltage range VCO tuning input gain Synthesizer External reference input frequency Sinusoidal input signal level (RMS value) Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter Phase Detector Phase detector comparison frequency Charge-pump Output Charge-pump output current Leakage current Timing Conditions (1)(2) Over full temperature range(1) VVTUNE GVCO D7 = 0 D7 = 1 AC coupled sinewave 2400 0.5 150 10.368 13.824 250 32/33 86/87/88/89 0 2483 VCC - 0.5 MHz V MHz/V MHz MHz REF_CLK REF_CLK SPSC SMC SSC 500 mVRMS 31 fPD 1728 kHz VCP = 1/2 VCC VCP = 1/2 VCC ICP IL TX RX-time RX TX-time CS-time PD TR-time PD RX-time PRR-time PLL set-time 2 100 100 100 350 450 400 3 350 1.4 -0.3 0 -5 +5 10 3.4 +0.4 3.4 mA pA s s s s s s s V V V V A MHz 10.1 Transmit to Receive time 10.2 Receive to Transmit time 10.3 Channel switch time 10.4 Power down to Transmit 10.5 Power down to Receive 10.6 Programming register 10.7 PLL settling time 11 11.1 HIGH-level input voltage 11.2 LOW-level input voltage 11.3 HIGH-level output voltage 11.4 LOW-level output voltage 11.5 Input bias current 11.6 3-wire bus clock frequency Notes: Logic 1 Logic 0 Logic 1 Logic 0 Logic 1 or logic 0 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE VIH VIL VOH VOL Ibias fCLKmax 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For further information refer to Application Note. 7 4779F-ISM-09/04 PLL Principle Figure 3. PLL Principle Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = 1728 kHz x (SMC x 32 + SSC) External loop filter Phase frequency detector PD fPD = 1728 kHz PA driver Charge pump VCO Divider by 2 Mixer Gaussian filter GF Reference counter RC REF_CLK 10.368 MHz 13.824 MHz D7 0 1 PLL reference Frequency REF_CLK Baseband controller TXDAT 8 ATR2406 [Preliminary] 4779F-ISM-09/04 ATR2406 [Preliminary] The following table shows the LO frequencies for RX and TX in the 2.4 GHz ISM band. There are 95 channels available. Since the ATR2406 supports wideband modulation with 400 kHz deviation, every second channel can be used without overlap in the spectrum. Table 1. LO Frequencies Mode fIF/kHz Channel C0 C1 TX ... C93 C94 C0 C1 RX 864 ... C93 C94 fANT/MHz 2401.056 2401.920 ... 2481.408 2482.272 2401.056 2401.920 ... 2481.408 2482.272 fVCO/MHz 2401.056 2401.920 ... 2481.408 2482.272 2401.920 2402.784 ... 2482.272 2483.136 SMC 86 86 ... 89 89 86 86 ... 89 89 SSC 27 28 ... 24 25 28 29 ... 25 26 N 2779 2780 ... 2872 2873 2780 2781 ... 2873 2874 TX Register Setting MSB Data bits D15 0 D14 1 D13 PA D12 The following 16-bit word has to be programmed for TX. LSB D11 D10 GFCS D9 D8 1 D7 RC D6 MC D5 D4 D3 D2 SC D1 D0 Note: D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0 or 1. Table 2. Output Power Settings with Bits D12 - D13 PA (Output Power Settings) D13 0 0 1 1 D12 0 1 0 1 RAMP_OUT (Pin 21) 1.3 V 1.35 V 1.4 V 1.75 V 9 4779F-ISM-09/04 RX Register Setting Register Setting without Clock Recovery MSB Data bits D15 0 D14 1 D13 X D12 X The are two RX settings possible. For a data rate of 1152 kBit/s an internal clock recovery function is implemented. Must be used for data rates below 1.152 Mbit. LSB D11 X D10 X D9 X D8 0 D7 RC D6 MC D5 D4 D3 D2 SC D1 D0 Note: X values are not relevant and can be set to 0 or 1. RX Register Setting with Internal Clock Recovery Recommended for 1.152 Mbit data rate. The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal samples the data signal. MSB Data bits D24 1 D23 0 D22 1 D21 0 D20 0 D19 0 D18 0 D17 0 D16 0 LSB D15 0 D14 0 D13 X D12 X D11 X D10 X D9 X D8 0 D7 RC D6 MC D5 D4 D3 D2 SC D1 D0 Note: X values are not relevant and can be set to 0 or 1. PLL Settings RC, MC and SC bits are controlling the synthesizer frequency according to Table 3, Table 4 and Table 5. Formula for calculating the frequency: TX frequency: fANT = 864 kHz x (32 x SMC + SSC) RX frequency: fANT = 864 kHz x (32 x SMC + SSC + 1) Table 3. PLL Settings with the Reference Counter Bit D7 RC (Reference Counter) D7 0 1 CLK Reference 10.368 MHz 13.824 MHz 10 ATR2406 [Preliminary] 4779F-ISM-09/04 ATR2406 [Preliminary] Table 4. PLL Settings with the Main Counter Bits D5 - D6 MC (Main Counter) D6 0 0 1 1 D5 0 1 0 1 SMC 86 87 88 89 Table 5. PLL Settings with the Swallow Counter Bits D0 - D4 SC (Swallow Counter) D4 0 0 0 ... 1 1 1 D3 0 0 0 ... 1 1 1 D2 0 0 0 ... 1 1 1 D1 0 0 1 ... 0 1 1 D0 0 1 0 ... 1 0 1 SSC 0 1 2 ... 29 30 31 GFCS Adjustment The Gaussian Filter Control Setting is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. These bits are only relevant in TX mode. Table 6. GFCS Adjustment with Bits D9 - D11 GFCS (Gaussian Filter Control Settings) D11 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 D9 0 1 0 1 0 1 0 1 GFCS 60% 70% 80% 90% 100% 110% 120% 130% The VRAMP voltage is used to control the output power of an external power amplifier. The voltage ramp is started with the TX_ON signal. These bits are only relevant in TX mode. 11 4779F-ISM-09/04 Control Signals The various transceiver functions are activated by the following control signals. A timing proposal is given in Figure 5 on page 13 Table 7. Control Signals - Functions Signal PU_REG PU_TRX RX_ON TX_ON nOLE Functions Activates AUX voltage regulator and the VCO voltage regulator supplying the complete transceiver Activates RX/TX blocks Activates RX circuits: DEMOD, IF AMP, IR MIXER Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT Disables open loop mode of the PLL Serial Programming Bus The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed information is active. Additional leading bits are ignored and there is no check made how many clock pulses arrived during enable low condition. The programming of the transceiver is done by a 16 bit or 25 bit data word (for the RX clock recovery mode). 3-wire BUS Timing Figure 4. 3-wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TPER TL TS TC TH TEC TT Table 8. 3-wire Bus Protocol Table Description Clock period Set time data to clock Hold Time data to clock Clock pulse width Set time enable to clock Hold time enable to data Time between two protocols Symbol TPER TS TH TC TL TEC TT Minimum Value 100 20 20 60 100 0 250 Unit ns ns ns ns ns ns ns 12 ATR2406 [Preliminary] 4779F-ISM-09/04 ENABLE Pin 32 nOLE Pin 26 REF_CLK > 50 s Signals to TRX (Input) Signals from TRX (Output) 4779F-ISM-09/04 C2 Power-up Programming Active RX-slot Programming Active TX-slot Power-down C3 C4 C1 C2 C3 C5 C1 Power-down optional Power-up optional > 40 s > 50 s > 40 s C1 MODE Pin Name Power-down PU_REG Pin 1 PU_TRX Pin 27 Figure 5. Complete TX and RX Timing Diagram TX_DATA Pin 29 Data CLOCK Pin 30 16/25 bits > 350 s 16 bits > 350 s DATA Pin 31 REF_CLK Pin 2 REF_CLK RX_ON Pin 24 TX_ON Pin 25 Data RX_DATA Pin 28 valid signal VS 0V VS 0V RSSI Pin 3 ATR2406 [Preliminary] RAMP_OUT Pin 21 connected to RAMP_IN of optional PA 13 Table 9. Description of the Conditions/States Conditiion C1 Description Power-down ATR2406 is switched off and the supply current is lower than 1 A. Power-up ATR2406 is powered up by toggling PU_REG and PU_RTX to high. PU_REG enables the external AUX-Regulator transistor and PU_TRX enables the internal regulator like VCO_REG (VCO supply voltage regulator) as well as wakes up the PLL, the VCO, the demodulator, mixer, etc. It is necessary to wait at least 40 s until the different supply voltage regulators have settled. Programming Via the tree-wire-interface the internal register of ATR2406 is programmed. At TX, this is just the PLL (transmit channel) and the deviation (gaussian filter). At RX, this is just the PLL (receive channel) and if the clock recovery is used also the bits to enable this option. At start of the three-wire-programming, the enable signal is toggled from high to low to enable clocking the data into the internal register. When the enable signals rises again to high, the programmed data is latched. This is the time point at which the settling of the PLL is starting. It is necessary to wait the settling time of 350 s so that the VCO-Frequency is stable. The reference clock needs to be applied to ATR2406 at minimum the time when the PLL is in operation - which is the programming state (C3) and the active slot (C4, C5). Out of the reference clock, several internal signals are also derived, i.e., the gaussian filter circuitry and TX_DATA sampling. This is the receive slot where the transmit burst is received and data as well as recovered clock are available. This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the signal nOLE toggles to low which enables modulation in open-loop-mode. C2 C3 C4 C5 Received Signal Strength The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is shown in Figure 6. Indication RSSI Figure 6. Typical RSSI Value versus Input Power 2.5 2.0 RSSI Level (V) 1.5 1.0 0.5 0.0 -130 -110 -90 -70 -50 -30 -10 10 RF Level (dBm) 14 ATR2406 [Preliminary] 4779F-ISM-09/04 TX_DATA RX_DATA PU_TRX nOLE TX_ON RX_ON RAMP_OUT VBATT ENABLE DATA CLOCK J24 R1 NC RX-CLOCK RSSI REF_CLK PU_REG C11 18p 32 31 30 29 28 27 26 25 IC2 C9 24 RX_ON TP1 DATA CLOCK ENABLE PU_TRX C6 C7 2p2 2p2 C3 TX_DATA 3 IC 22 21 20 19 C10 18 17 1p8 J1 TP2 RAMP_OUT TX_OUT RX_IN1 RX_IN2 5 VS_IFD VS_IFA ATR2406 6 RX-CLOCK 7 VREG_VCO VTUNE 8 IC CP VREG VS_REG REG_DEC C24 9 10 15 13 11 12 14 16 G C16 4p7 R3 62k REG_CTRL VS_SYN GND IREF VS_TRX Strip 3n3 4 RSSI RX_DATA REF_CLK IC 1p5 1p8 2 23 TX_ON PU_REG nOLE 1 Strip 4n7 C23 C4 C17 NC 390p C14 100n NC R6 820 R4 C19 470n C13 C21 C20 22n 2n2 C18 68p 1k5 VS J2 GND2 GND7 GND8 GND9 GND4 GND5 GND6 GND1 GND3 4779F-ISM-09/04 RFOUT (Ant) Select integrated F-antenna or SMA connector by setting the 0R resistor ANT2 F-antenna ANT ANT NC GND GND R2 Application Circuit Figure 7. Application Circuit C1 SMASI 5p6 J2 Strip Lowpassfilter J11 VBATT 47 VBATT TX_ON TX_DATA PU_TRX CLOCK RX_ON J8 J9 J4 J5 J6 J7 C15 J12 J13 J14 J15 J16 J17 RSSI J10 3k3 J3 R5 ENABLE DATA nOLE PU_REG RX-CLOCK RX_DATA C12 BC808 Strip-balun REF_CLK T1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 100n VLSI Connector J18 J19 J20 J21 47 C20, C21, COG dielectric Slug RAMP ATR2406 [Preliminary] The ATR2406 requires only few low cost external components for operation. A typical application is shown in Figure 7. J26 IC2P GND 15 PCB-layout Design Figure 8. PCB-layout ATR2406-DEV-BOARD 16 ATR2406 [Preliminary] 4779F-ISM-09/04 ATR2406 [Preliminary] Table 10. Bill of Material Part C1 C3 C4 C5 C6 C7 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C23 C24 L6 R3 R4 R5 R6 IC2 T1 MSUB Note: Value 5p6 1p8 390p 4p7 2p2 2p2 1p5 1p8 18P 100n 47 1n 100n 47 3n3 68p 470n Part Number Vendor Package 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 3216 0402 0402 3216 0402 0402 0402/0603 0805 0603 0402 0402 0402 0402 0402 0402 0402 MLF32 (R) Comment GJM1555C1H5R6CB01 or GRM1555C1H5R6DZ01 Murata(R) GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata GRM1555C1H391JA01 Murata GJM1555C1H4R7CB01 or GRM1555C1H4R7CZ01 Murata GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata GJM1555C1H1R5CB01 or GRM1555C1H1R5CZ01 Murata GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata GRM1555C1H180JB01 GRM15F51H104ZB01 B45196H2475M109 GRM15R71H102KB01 GRM15F51H104ZB01 B45196H2475M109 GRM15R71H332KB01 GRM155C1H680JB01 GRM18F51H474ZB01 (0402) or 0603-Version Murata Murata Epcos(R) Murata Murata Epcos Murata Murata Murata Murata Murata Murata Murata Wurth Electronic(R) Vishay(R) Vishay Vishay Vishay Atmel Vishay, Philips , ... NC Optional2 NC Optional2 NC 22n, COG GRM21B5C1H223JA01 2n2, COG GRM1885C1H222JA01 4n7 4p7 8n2 62k 1k5 3k3 820R ATR2406 BC808-40 FR4 1 GRM15R71H472KB01 GRM1555C1H4R7CB01 WE-MK0402 744784082 62k, 5% 1k5, 5% 3k3, 5% 820R, 5% ATR2406 BC808-40, any standard type can be used, important is "-40" NC, Strip used Ref_Clk-Level, optional1 Ref_Clk-Level, optional1 SOT-23 Optional2 FR4, e_r = 4.4 at 2.45 GHz, H = 500 m, T = 35 m, tand = 0.02, surface i.e. chem. tin or chem. gold Option = no necessary if supplied RefClk level is within specification range Option2 = if no AUX regulator is used, then T1 has to be bypassed To use the integrated F-antenna, set jumper R2 (0R resistor 0603) Table 11. Parts Count Bill of Material Parts Count Capacitors 0402 Capacitors >0402 Resistors 0402 Inductors 0402 Semiconductors Required (Minimal BOM) 14 2 2 1 Optional (Depending on Application) 2 2 1 17 4779F-ISM-09/04 Ordering Information Extended Type Number ATR2406-PNSG ATR2406-PNQG ATR2406-DEV-BOARD ATR2406-DEV-KIT Package QFN32 - 5x5 QFN32 - 5x5 Remarks Tube, Sampling; Pb-free Taped and reeled; Pb-free RF-module Complete Evaluation-kit MOQ 600 6000 1 1 Package Information 18 ATR2406 [Preliminary] 4779F-ISM-09/04 ATR2406 [Preliminary] Recommended Footprint/Landing Pattern Figure 9. Recommenced Footprint/Landing Pattern Table 1. Recommended Footprint/Landing Pattern Signs Sign A B C a b c d e Size 3.2 mm 1.2 mm 0.3 mm 1.1 mm 0.3 mm 0.2 mm 0.55 mm 0.5 mm 19 4779F-ISM-09/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2004. All rights reserved. Atmel (R) and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. EPCOS (R) is a registered trademark of Siemens Aktiengesellschaft CORPORATION FED REP GERMANY. Murata (R) is a registered trademark of Murata Manufacturing Co., Ltd. CORPORATION Japan. Philips (R) is a registered trademark of Koninklijke Philips Electronics N.V. Vishay (R) is a registered trademark of Vishay Intertechnology, Inc. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4779F-ISM-09/04 |
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